With increasing popularity of electronic devices, such as laptop computers, portable digital assistants, digital cameras, mobile phones, digital audio players, video game consoles and the like, demand for nonvolatile memories are on the rise. Nonvolatile memories come in various types, including flash memories. Flash memories are widely used nowadays for fast information storage in electronic devices such as those mentioned above. A flash memory cell is generally programmed by storing charge on a charge storage structure, such as a charge trap or a floating gate. The charge may thereafter remain on the charge storage structure for an indefinite period even after power has been removed from the flash memory device. Flash memory devices are therefore non-volatile.
Charge is stored on the charge storage structure (referred to hereinafter by example as a “floating gate”) by applying appropriate voltages to the control gate and the drain or source. For example, negative charge can be placed on the floating gate by grounding the source while applying a sufficiently large positive voltage to the control gate to attract electrons, which tunnel through the gate oxide to the floating gate from the channel region.
A flash memory cell can be read by applying a voltage to the control gate that is positive with respect to the source. The amount of charge stored on the flash memory cell determines the magnitude of the voltage that must be applied to the control gate to allow the flash memory cell to conduct current between the source and the drain. As negative charge is added to the floating gate, the threshold voltage of the flash memory cell increases thus increasing the magnitude of the voltage that must be applied to the control gate to allow the flash memory cell to conduct current. During a read operation, a read voltage is applied to the control gate that is large enough to render the cell conductive if insufficient charge is stored on the floating gate, but not large enough to render the cell conductive if sufficient charge is stored on the floating gate. During the read operation, the drain, which is used as the output terminal of the cell, is precharged to a positive voltage, and the source is coupled to ground. Therefore, if the floating gate of the flash memory cell is sufficiently charged, the drain will remain at the positive voltage. If the floating gate of the flash memory cell is not sufficiently charged, the cell will ground the drain.
Before a flash memory cell can be programmed, it may be erased by removing charge from the floating gate. The cell can be erased by applying a gate-to-source voltage to the cell that has a polarity opposite that used for programming. For example, the control gate can be grounded, and a large positive voltage applied to the source to cause the electrons to tunnel through the gate oxide and deplete charge from the floating gate. In another approach, a relatively large negative voltage is applied to the control gate, and a positive voltage, such as a supply voltage, is applied to the source region.
A typical flash memory device includes a memory array containing a large number of flash memory cells arranged in rows and columns. Two common types of flash memory array architectures are the “NAND” and “NOR” architectures, so called for the logical form in which the basic flash memory cell configuration of each is arranged. A typical flash memory array may include a large number of flash memory cells divided into a number of blocks. Each block may include a number of rows, with the cells in the same row having their control gates coupled to a common word line. Cells in the same column may have their sources and drains connected to each other in series. Thus all of the memory cells in the same column of each block are typically connected in series with each other. The drain of the upper flash memory cell in the block is coupled to a bit line through a select gate transistor. Each of the bit lines output a respective bit line signal BL1-BLN indicative of the data bit stored in the respective column of the array. The bit lines may extend through multiple blocks to respective sense amplifiers.
The storage capacity of a flash memory array can be increased by storing multiple bits of data in each flash memory cell. This can be accomplished by storing multiple levels of charge on the floating gate of each cell. These memory devices are commonly referred to as multi-bit or multi-level flash memory cells, known as “MLC memory cells.” In MLC cells, multiple bits of binary data corresponding to distinct threshold voltage levels defined over respective voltage ranges are stored within a single cell. Each distinct threshold voltage level corresponds to a respective combination of data bits. Specifically, the number N of bits requires 2N distinct threshold voltage levels. For example, for a flash memory cell to store 2 bits of data, 4 distinct threshold voltage levels corresponding to bit states 00, 01, 10, and 11 are needed. When reading the state of the memory cell, the threshold voltage level for which the memory cell conducts current corresponds to a combination of bits representing data programmed into the cell. The two or more bits stored in each flash memory cell may be adjacent bits in the same page of data. However, more frequently, one bit is treated as a bit in one page of data, and the other bit is treated as the corresponding bit in an adjacent page of data. The bit states assigned to respective charge levels are normally the same for all rows of memory cells in an array. The bit states assigned to the flash memory cells in the array are usually implemented in hardware and thus cannot be changed during operation of the flash memory device.
FIG. 1 is a schematic illustration of a memory layout 100 including two memory arrays 102, 104 according to the prior art. The memory arrays 102, 104 may include any number and arrangement of memory cells. Each memory array 102, 104 is connected to a corresponding multiplexor region 106, 108. The multiplexor regions 106, 108 include circuitry for coupling selected blocks of the memory arrays 102, 104 to other components of the memory 100. High voltage isolation regions 110, 112 are provided which include circuitry for isolating the higher voltages which may be used in the memory arrays 102, 104 and/or the multiplexor regions 106, 108 from other components.
A dynamic data cache (DDC) region 114 is included which contains circuitry for dynamic data caches. The dynamic data caches may temporarily store data sensed from the memory arrays 102 and 104 or data that will be programmed into the memory arrays 102 and 104. As shown in FIG. 1, the dynamic data cache region 114 includes, for example, sixteen dynamic data caches. The sixteen dynamic data caches may be shared between the top and bottom memory arrays 102, 104. In other examples, eight dynamic data caches may be used. Region 116 includes circuitry for interacting with the memory arrays 102, 104 and/or DDCs 114, including a data detector, column knock-out latch, and a column select (csl) decoder. The column select decoder may provide appropriate signals to the DDCs in the DDC region 114 to select a particular DDC and allow sensed data to be stored therein, or allow the data stored therein to be programmed into the connected memory array.
FIG. 2 is a schematic illustration of portions of the memory of FIG. 1 showing additional detail. The memory array 102 includes sixteen pairs of even and odd bit lines, labeled ble0/blo0 through ble15/blo15. The multiplexer region 106 includes corresponding pairs of bias transistors 206(1) through 206(32). The bias transistors are configured to receive a bias signal at one source/drain terminal while the bit line is connected to the other source/drain terminal. The bias transistors receive either an even bias signal, blbiase, or an odd bias signal, blbiaso, at their gate terminal. The bit lines are further coupled to a source/drain terminal of a respective select transistor, 207(1) through 207(32). The select transistors 207(1-32) each receive either an odd select signal, blso, or an even select signal, blse, at their gate terminal. The blse/blso signals will select whether an even or odd bit line will be coupled to the isolation transistor. Each pair of select transistors is coupled to a respective isolation transistor within the isolation region 110. The isolation transistors 210(1)-210(16) receive an isolation signal, hviso, at their gate terminal. Accordingly, the isolation transistors 210(1)-210(16), when on, couple a selected even or odd bit line through to a DDC.
The DDC region 114 includes sixteen DDCs, labeled DDC<0> through DDC<15>. Each pair of bit lines of the memory array 102 is coupled to one of the DDCs. Each pair of bit lines of the memory array 104 is also coupled to one of the DDCs. Accordingly, the data lines 250, dw<0>, extending from the transistor 210(1) and serving the bit lines ble0 and blo0 traverses the entire length of the DDC region 114 to connect to bit lines in the memory array 104. Similarly, the data line 252, dw<15> extending from the transistor 210(16) traverses the entire length of the DDC region 114 to connect to bit lines in the memory array 104.
Column select lines, such as the csl line 260, and data verify lines, such as the dvrfy line 262 are provided for each byte of data lines to couple data stored in the DDCs to and from the two sets of data output lines dataio<0>-dataio<7> as shown. That is, for each eight data lines, one csl line and one dvrfy line are provided in the embodiment of FIG. 2. Accordingly, for each byte of data, eight data lines dw<0> through dw<7>, one csl line, and one dvrfy line are required, for a total of 10 lines per byte of data.
The dvrfy line is used to check a fail bit during programming and verify operations of the memory device. A primary data cache in the dynamic data caches may store the pass or fail bit information during the operation. In this manner, data may be verified and, if the data has failed, a fail bit may indicate that the data is not good.